Improving reliability of non-volatile memory technologies through circuit level techniques and error control coding
© Yang et al.; licensee Springer. 2012
Received: 16 April 2012
Accepted: 20 August 2012
Published: 3 October 2012
Non-volatile resistive memories, such as phase-change RAM (PRAM) and spin transfer torque RAM (STT-RAM), have emerged as promising candidates because of their fast read access, high storage density, and very low standby power. Unfortunately, in scaled technologies, high storage density comes at a price of lower reliability. In this article, we first study in detail the causes of errors for PRAM and STT-RAM. We see that while for multi-level cell (MLC) PRAM, the errors are due to resistance drift, in STT-RAM they are due to process variations and variations in the device geometry. We develop error models to capture these effects and propose techniques based on tuning of circuit level parameters to mitigate some of these errors. Unfortunately for reliable memory operation, only circuit-level techniques are not sufficient and so we propose error control coding (ECC) techniques that can be used on top of circuit-level techniques. We show that for STT-RAM, a combination of voltage boosting and write pulse width adjustment at the circuit-level followed by a BCH-based ECC scheme can reduce the block failure rate (BFR) to 10–8. For MLC-PRAM, a combination of threshold resistance tuning and BCH-based product code ECC scheme can achieve the same target BFR of 10–8. The product code scheme is flexible; it allows migration to a stronger code to guarantee the same target BFR when the raw bit error rate increases with increase in the number of programming cycles.
KeywordsMLC PRAM STT-RAM Circuit level techniques Error control coding Block failure rate
Over the last decade, there has been a significant research effort on designing different types of memory devices that have high data storage density and low leakage power. Many of these works focus on finding an alternative to commonly used SRAM, DRAM, and Flash memories[1, 2]. The two most attractive memory technologies that have emerged are phase-change RAM (PRAM)[3, 4] and spin transfer torque RAM (STT-RAM)[5–7]. STT-RAM is an attractive candidate for lower level caches because of its fast read and write operation, very low standby power, and high endurance. PRAM, on the other hand, is a promising candidate for high-level cache and external storage due to high density and very low standby power. While single level cell (SLC) PRAM and STT-RAM have comparable memory densities, multi-level cell (MLC) PRAM has been introduced to improve the memory density even further[8, 9]. Unfortunately, MLC-type memories have reliability issues that need to be addressed.
The two competing memory technologies operate in very different ways. While in PRAM, data are stored as a resistance value set by thermal constraints, whereas in STT-RAM it is set by the magnetization angle. The PRAM cell changes between amorphous phase (low resistance) and crystalline phase (high resistance); the value that is stored in the cell is a function of this resistance. The resistance in STT-RAM is a function of the magnetization angle of the magnetic tunneling junction (MTJ). The value that is stored in the cell is based on whether the direction of the magnetization angle is parallel (P) (bit ‘0’) or antiparallel (AP) (bit ‘1’).
As the technology of these emerging memory devices become more mature and they get ready to be adopted in mainstream computers, a study of their reliability becomes very important. The causes of errors of these two technologies and the techniques that can be used to mitigate them are quite different. For instance, MLC PRAM which has very high storage density has higher error rate because of reduced difference between consecutive resistance levels. The resistance of an intermediate state drifts to that of a state with higher resistance causing soft errors; these errors increase with data storage time. Again the resistance of the amorphous state decreases with the number of programming cycles and causes hard errors. Resistance drift has been studied and a technique to tune the threshold resistance between adjacent states to handle soft errors has been proposed in[11, 12]. We analyze the effect of threshold resistance on the total error rate (combination of hard and soft error rates) and show that there is an optimal threshold value for a given data storage time and number of programming cycles. This threshold value can be adjusted using circuit-level techniques to reduce bit error rate (BER) to 10–4.
The source of errors in STT-RAM is quite different from that of PRAM[13–15]. Majority of the errors are due to process variations[13, 15]. These include variation of the access transistor sizes (W/L), variation in Vth due to random dopant fluctuation (RDF), MTJ geometric variation and thermal fluctuations that are modeled using change in initial magnetization angle of the MTJ. BER due to these variations can be as high as 10–1 for write-1 operation. Fortunately, the error rate can be dropped to 10–5 by circuit-level techniques such as adjusting W/L ratio of the access transistor, changing the current pulse width during write, and increasing the voltage across the STT-RAM cell.
Apart from the purely circuit-level techniques, hybrid techniques that consist of circuit techniques followed by error control coding (ECC) have also been proposed to increase the reliability of both PRAM and STT-RAM. For instance for MLC PRAM, Xu and Zhang proposed a hybrid technique that first reduced the soft error rate by adjusting the threshold resistance and then used BCH or LDPC codes on large code words to improve the reliability with high storage efficiency. Since this technique is for mass storage devices, the large latency is not a concern. Another hybrid technique for MLC PRAM has been proposed in where architecture-level techniques such as subblock flipping and bit interleaving followed by BCH(t = 3) codes have been applied on top of threshold resistance tuning. For STT-RAM, Sun et al. proposed a combination of write-read-verify strategy and Hamming codes to protect against write errors in cache. While the write-read-verify strategy increases the latency and energy, it reduces the error rate significantly and as a result it is sufficient to use simple ECC such as Hamming codes.
In this article, we first study the causes of errors in MLC PRAM and STT-RAM starting from first principles and model the probability of hard and soft errors. In each case, we show how circuit-level techniques can reduce some of the errors. Next, we show how traditional ECC techniques can be used in conjunction with the circuit techniques to further improve the error rate. For instance, for STT-RAM. a combination of circuit parameter tuning and BCH code-based ECC can help achieve block failure rate (BFR) of 10–8. For PRAM, a combination of threshold resistance tuning and BCH-based product code scheme can achieve the same target BFR. In addition, the proposed product code scheme has the capability to migrate to a stronger ECC when the error rate increases with increase in the number of programming cycles. This study is an extension of[16, 17]. The specific contributions of this article are as follows.
A detailed analysis of errors in MLC PRAM due to resistance drift as a function of data-storage time and number of programming cycles.
Determination of optimal resistance threshold value that minimizes the overall error rate (hard and soft) for MLC PRAM.
A detailed study of process variation induced failures in STT-RAM.
Development of circuit-level techniques for STT-RAM that reduces the error rate due to judicious use of increase in W/L ratio of the access transistor, higher voltage difference across the memory cell, and pulse width adjustment in write operation.
Development of ECC techniques for both MLC-PRAM and STT-RAM that can be used in conjunction with circuit-level techniques to further enhance the reliability. Evaluation of the hardware overhead and error correction performance of the different techniques.
The rest of the article is organized as follows. “PRAM reliability” section describes the sources of soft and hard errors for 2-bit MLC PRAM and proposes circuit-level techniques to reduce them. “STT-RAM reliability” section describes the causes of failures in STT-RAM and proposes circuit parameter tuning to address them. “ECC schemes” section focuses on the details of the ECC schemes for PRAM and STT-RAM with hardware overhead. Finally, the article concludes with some conclusions.
In this section, we describe the basic structure of the PRAM cell including read and write operations (see “Background” section), characterization of its soft errors and hard errors (see “PRAM error model” section), and a circuit-level technique to reduce these errors (see “Circuit-level techniques for reducing soft and hard errors” section).
Unlike conventional SRAM and DRAM technologies that use electrical charge to store data, in PRAM, the logical value of data corresponds to the resistance of the chalcogenide-based material in the memory cell. Chalcogenide-based material is one of the phase-change materials which can switch between a crystalline phase (low resistance) and an amorphous phase (high resistance) with the application of heat. In PRAM, Ge2Sb2Te5 (GST) is usually used as the phase-change material.
To simulate the programming process of a PRAM cell, an HSPICE model has been developed as shown in Figure2b. According to this model, the equivalent circuit of PRAM consists of four parts: input energy conversion, temperature transition, phase change, and geometry. Here R T and C T represent the thermal resistance and capacitance of GST structure, Rwrite is the electrical resistance of GST during programming, Rm and Rg(T) represent the phase of GST material, and Cstate represents the state of the MLC cell. The geometry block describes the cross-sectional shape (mushroom) of the PRAM cell, the dimensions of which are used to calculate the electrical and thermal parameters. The input energy changes the temperature of GST material based on R T and C T . The temperature evaluated by the temperature transition block is used to decide on the switch position; when the temperature is higher than the melting temperature, the switch flips up and Cstate is charged by the voltage source, indicating the melting of GST, which results in the amorphous phase. When the temperature is between the melting and annealing temperature, the switch flips down and Cstate is discharged through Rg, indicating the annealing of GST, which results in the crystalline phase.
To increase the storage density of memory, MLC is used to store more than 1 bit within a single memory cell[8, 9]. Since the resistance between the amorphous and crystalline phases can exceed two to three orders of magnitude, multiple logical states corresponding to different resistance values can easily be accommodated. To study the programming process of MLC PRAM, the simulation model of SLC PRAM in Figure2b can still be utilized. Note that while for SLC PRAM, the switch between R m and Rg(T) can only be set to “R m ” or “Rg(T)” corresponding to amorphous or crystalline phase, for MLC PRAM, the switch is set to an intermediate position between the two ends.
Simulation parameters of a 2-bit MLC PRAM
2-bit MLC PRAM
CMOS current driver
PRAM error model
Sources of soft and hard errors
The reliability of a PRAM cell can be analyzed with respect to data retention, cycling endurance, and data disturb. Data retention represents the capability of storing data reliably over a time period and data retention time is the longest time that the data can be stored reliably. We define ‘storage time’ as the time that the data are stored in memory between two consecutive writes. Thus, the storage time has to be less than the data retention time. For PRAM, data retention depends on the stability of the resistance in the crystalline and amorphous phases. While the crystalline phase is fairly stable with time and temperature, the amorphous phase suffers from resistance drift and spontaneous crystallization. Initially, the resistance increases due to structure relaxation (SR), a phenomenon seen in amorphous chalcogenides and related to the dynamics of the intrinsic traps. Eventually, crystallization in the amorphous phase results in a drop in resistance and thereby loss of data in the cell. SR of the amorphous phase affects both resistance and threshold voltage of amorphous phase. However, since the read region of the voltage is usually below the threshold voltage, only resistance drift is studied in this article. Resistance drift results in soft errors as will be described shortly.
Hard errors occur when the data value stored in one cell cannot be changed in the next programming cycle. There are two types of hard errors in PRAM: stuck-RESET failure and stuck-SET failure. Stuck-SET or stuck-RESET means that the value of stored data in PRAM cell is stuck in SET or RESET state no matter what value has been written into the cell. These errors increase as the number of programming cycles increases.
Data disturb, known as proximity disturb, can occur in a cell in RESET state if surrounding cells are repeatedly programmed. In this case, the heat generated during the programming operation diffuses from the neighboring cells and accelerates crystallization. Another type of disturb, read disturb, occurs when a cell is read many times. This type of disturb is dependent upon the applied cell voltage and ambient temperature. Both these types of disturb are not as prevalent and so in the rest of this section we focus on the effects of data retention and cycling endurance on the error rate.
Parameters of resistance drift model
In a stuck-RESET failure, the device resistance suddenly and irretrievably spikes, entering a state that has much higher resistance than the normal RESET state. Stuck-RESET can also be caused by over programmed current. Higher programming current results in larger amorphous volume, which takes more time to become crystalline, shows higher resistance than desired value after a SET operation.
Circuit-level techniques for reducing soft and hard errors
In the previous section, we have shown that the soft error rate increases with data storage time and that the hard error rate increases with the number of programming cycles. In this section, we show how the error rate can be controlled by tuning the threshold resistance Rth(00,01) for a specific data storage time. Recall that threshold resistance can be tuned by changing the current reference of the sense amplifier. Data storage time is set to 105 s, which is typical of storage systems such as those for daily backup.
However, if data storage time distribution is known a priori, then a better estimate of this time can be used to derive the threshold resistance.
Soft error rate
The soft error rate of 2-bit MLC PRAM is a function of the resistance drift of ‘01’ to ‘00’ state, Es (‘01’- > ‘00’), and the resistance drift of ‘10’ to ‘01’ state, Es (‘10’- > ‘01’). While Es (‘01’- > ‘00’) depends on the value of Rth(01,00), Es (‘10’- > ‘01’) depends on the value of Rth(10,01).
In order to counteract the effect of resistance drift, dynamic Rth(01,00) and Rth(10,01) tuning has been proposed in. Here, a time tag is used to record the storage time information for each memory block or page and this information is used to determine the threshold resistance that minimizes the BER. The technique in considers the effect of resistance drift on soft errors. The threshold resistance value affects the hard error rate as well and so the choice of threshold resistance has to be determined by both soft and hard error rates as will be described next.
Hard error rate
The hard error rate of 2-bit MLC PRAM is due to the resistance drop of ‘00’ state to the ‘01’ state as shown in Figure7. It is a function of Rth(01,00), and the resistance distribution of state 00. Due to multiple pulse write strategy for intermediate states, there is no resistance drop from ‘01’ state to ‘10’ state, and thus Rth(10,01) has no impact on the hard error rate.
Total error rate
Tuning threshold resistance
In this section, we describe the basic structure of the STT-RAM cell including its read/write operations (see the next section), sources of its errors (see “STT-RAM error model” section), and circuit-level techniques to reduce them (see “Circuit-level techniques for reducing error ” section).
where is magnetic moment, μ0 is vacuum permeability, α is damping constant. Such an equation can be modeled using Verilog-A to simulate the circuit characteristics of STT-RAM. For instance, differential terms are modeled using capacitance while Zeeman and damping energy are described by voltage-dependent current source. The voltage of the capacitor indicates the evaluated state (magnetization angle) which is further translated to resistance of MTJ.
Consider the cell structure consisting of an access transistor in series with the MTJ resistance illustrated in Figure15c. The access transistor is controlled through WL, and the voltage levels used in BL and SL lines determine the current which is used to adjust the magnetic field. There are three modes of operation for an STT-RAM: write-0, write-1, and read. We distinguish between write-0 and write-1 because of the asymmetry in their operation. In general, directions of the current during write-0 and read operation are the same, while the magnitude of the current is fairly high (approximately 10×) during the write operation. For read operation, current (magnetic field) lower than critical current (magnetic field) is applied to MTJ to determine its resistance state. Low voltage (approximately 0.1 V) is applied to BL, and SL is set to ground. When the access transistor is turned on, a small current passes through MTJ whose value is detected based on a conventional voltage sensing or self-referencing schemes. During write operation, BL and SL are charged to opposite values depending on bit value that is to be stored. During write-0, BL is high and SL is set to zero, whereas during write-1, BL is set to zero and SL is set to high. The asymmetric structure of write-0 and write-1 operations motivates SL line to be higher than nominal during write-1 so that both operations generate comparable write-current. Such a circuit technique is elaborated in the next section.
STT-RAM error model
There are several factors that affect the failure in STT-RAM memories: access transistor manufacturing errors such as those due to RDFs, channel length, and width modulations, geometric variations in MTJ such as area and thickness variation, and thermal fluctuations that are modeled by the initial magnetization angle variation. Note that all these variations cause hard errors.
Apart from errors that are caused by process variations, MTJ also suffers from time-dependent reliability issues. MTJ structure consists of a very thin insulating layer (approximately 1 nm) and voltage across MTJ can approximately be 0.6–1 V. This results in a very high electric field across the thin insulator (approximately 10 MV/cm) which can cause time-dependent dielectric breakdown (TDDB). With high scaling, the electric field across insulating layer rises, thereby increasing the possibility of TDDB.
Device parameters of STT-RAM
Transistor channel length(nm)
Transistor channel width (nm)
96, 128, 160
Transistor threshold (RDF)
σ VT =40 mV
MTJ initial angle
Errors in read and write operations
The reliability of an STT-RAM cell has been investigated by several researchers. While Chatterjee et al. studied the failure rate of a single STT-RAM cell using basic models for transistor and MTJ resistance, process variation effects such as RDF and geometric variation were considered in[15, 28]. In this section, we also present the effects of process variation and geometric variation. We add the variation effects to the nominal HSPICE model of STT-RAM and use Monte Carlo simulations to generate the error rates caused by each variation.
BERs of a single STT-RAM cell
Read (Vread= 0.1 V)
Write (pulse width = 25 ns)
Approximately 4 × 10–5
Circuit-level techniques for reducing error
In this section, we show how W/L sizing of access transistor, voltage boosting, and pulse width adjustment can be used to improve the reliability of the STT-RAM cell. Access transistor sizing has been investigated in[7, 13], effect of process variation as well as write pulse width has been studied in[13, 14, 28] and voltage boosting of WL has been considered in[13, 29]. Here, we also study the read reliability and investigate the effect of combination of write pulse width and voltage boosting on the write reliability.
Effect of W/L of access transistor
Effect of voltage boosting
Effect of combination of voltage boosting and write pulse width duration
In general, increasing these parameters reduces BER, but causes higher energy consumption per operation. For instance, let the average BER (read/write combined) after circuit-level techniques be set to 10–5. From read failure analysis, we see that W/L = 4 achieves approximately BER = 10–5. Even though, increasing W/L ratio improves the reliability for both read and write operations, it reduces the cell density and increases the energy consumption. Thus, it should be applied with caution and other options investigated.
One of the effective techniques to reduce the error rate in memories is through ECC. As described in “PRAM reliability” and “STT-RAM reliability” sections, raw error rate of MLC PRAM and STT-RAM can significantly be reduced using circuit-level techniques. For instance, the error rate of MLC PRAM can be reduced to 10–4 by adjusting Rth(10,00) and the error rate of STT-RAM can be reduced to 10–5 by voltage boosting and/or write pulse width adjustment.
where t is the correction strength of the ECC, and BER represents the raw error rate after applying circuit-level techniques.
In this article, the target BFR is set to 10–8. For STT-RAM, this target is constant during the whole lifetime. For PRAM, the error rate increases with number of programming cycles. Our goal is to maintain the same BFR throughout the devices’ lifetime.
ECC scheme for STT-RAM and PRAM to achieve the target BFR
The raw error rate of MLC PRAM increases as the number of programming errors increases. Thus, a flexible ECC scheme that can support higher error correction capability over time is desirable. Flexible ECC scheme is implemented by using product code which corrects errors in two dimensions. When the number of programming cycles is low, it is sufficient to do ECC in one dimension. As the number of programming cycles increases, the flexible ECC scheme uses ECC in two dimensions to enhance the error correction capability.
Extra storage rates of different ECC schemes for three block sizes
BCH(78,64)*8+ even parity check
BCH(78,64)*16+ even parity check
BCH(144,128)*8+ even parity check
BCH(144,128)*16+ even parity check
BCH(274,256)*8+ even parity check
Synthesis results of all candidate BCH codes
Hardware overhead of ECC scheme for STT-RAM
Extra storage rate (%)
Hardware overhead of ECC scheme for MLC-PRAM
Extra storage rate (%)
In this article, we advocate the use of circuit parameter tuning and ECC to improve the reliability of emerging memory technologies such as MLC-PRAM and STT-RAM. We first analyze the error sources and build error models for these two technologies. Next we show that for MLC-PRAM, the hard and soft error rates can be reduced by optimal choice of threshold resistance. Similarly for STT-RAM, the hard error rate can be reduced by tuning the W/L ratios of the access transistors, boosting the voltage, and adjusting the write pulse width. These circuit-level techniques can help achieve BER of 10–4 to 10–5. For higher reliability, ECC techniques have to be used in conjunction with the circuit techniques. We show that for STT-RAM, it is sufficient to use a BCH code with t = 3 to achieve a BFR of 10–8. For MLC-PRAM, the raw BER increases with time and number of programming cycles and so a flexible ECC scheme that migrates to a stronger code is desirable. We propose one such product code scheme that uses BCH along rows and even parity along columns and achieves the desired BFR. We synthesize the ECC schemes in hardware and show that the hardware overhead, including additional storage, is quite low, making these schemes very attractive.
This study was supported in part by a grant from NSF, CSR 0910699, and CNS 1218183. The authors would like to acknowledge the assistance from Zihan Xu and Ketul Sutaria on the memory modeling work.
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