Area and power efficient DCT architecture for image compression

EURASIP Journal on Advances in Signal Processing

Table 4 Comparison of hardware resource consumption with the reported architectures for CMOS 90 nm ASIC implementation

Transform	Area (μm²)	Power (mW)			Critical path delay (ns)
		Leakage power	Dynamic power	Total power
SDCT[17]	3,892	0.0120	0.7251	0.7371	0.809
Bouguezel et al.[19]	4,042	0.0123	0.6725	0.6848	0.823
Bouguezel et al.[21]	2,864	0.0088	0.4249	0.4337	0.783
Bouguezel et al.[22]	3,787	0.0115	0.6662	0.6777	0.787
Bouguezel et al.[23] (a = 1)	2,907	0.0088	0.4354	0.4442	0.775
Senapati et al.[26]	2,273	0.0069	0.2799	0.2868	0.980
Cintra and Bayer[24]	3,072	0.0094	0.4541	0.4635	0.773
Bayer and Cintra[27]	2,221	0.0063	0.2687	0.2750	0.675
Transform in[29]	2,459	0.0077	0.3096	0.3173	0.103
Transform in[30]	2,301	0.0073	0.2831	0.2904	0.987
Proposed transform	1,954	0.0061	0.1893	0.1954	0.616