Verify level control criteria for multi-level cell flash memories and their applications
- Yongjune Kim^{1},
- Jaehong Kim^{2},
- Jun Jin Kong^{2},
- B V K Vijaya Kumar^{1}Email author and
- Xin Li^{1}
DOI: 10.1186/1687-6180-2012-196
© Kim et al.; licensee Springer. 2012
Received: 14 April 2012
Accepted: 17 August 2012
Published: 5 September 2012
Abstract
In _{1}M-bit/cell multi-level cell (MLC) flash memories, it is more difficult to guarantee the reliability of data as M increases. The reason is that an M-bit/cell MLC has 2^{ M } states whereas a single-level cell (SLC) has only two states. Hence, compared to SLC, the margin of MLC is reduced, thereby making it sensitive to a number of degradation mechanisms such as cell-to-cell interference and charge leakage. In flash memories, distances between 2^{ M } states can be controlled by adjusting verify levels during incremental step pulse programming (ISPP). For high data reliability, the control of verify levels in ISPP is important because the bit error rate (BER) will be affected significantly by verify levels. As M increases, the verify level control will be more important and complex. In this article, we investigate two verify level control criteria for MLC flash memories. The first criterion is to minimize the overall BER and the second criterion is to make page BERs equal. The choice between these criteria relates to flash memory architecture, bits per cell, reliability, and speed performance. Considering these factors, we will discuss the strategy of verify level control in the hybrid solid state drives (SSD) which are composed of flash memories with different number of bits per cell.
Introduction
Flash memory is now the fastest growing memory segment, driven by the rapid growth of mobile devices and solid state drives (SSD). To satisfy the market demand for lower cost per bit and higher density of nonvolatile memory, there are two approaches: (1) technology scaling, (2) multi-level cell (MLC)[1–4].
As the technology continues to scale down, flash memories suffer from more severe physical degradation mechanisms such as cell-to-cell interference (coupling) and charge leakage[5, 6]. In addition, M-bit/cell MLC flash memories have 2^{ M } states within the threshold voltage window whereas the single-level cell (SLC) has only two states. Therefore, the reliability of stored data is an important challenge for high density flash memories.
Therefore, positions of program states (except the erase state) are determined by verify levels and the tightness of each program state depends on the incremental step size ΔV_{ pp }. By reducing ΔV_{ pp }, the cell threshold voltage distribution can be made tighter, but the programming time will increase[7, 8]. In brief, ISPP can control both the distances between states by verify levels and the tightness of program states by the incremental step size.
For SLC, determining the verify level of the programming state is a simple problem because there is only one program state and the margin between the erase state and the program state is sufficiently large so that small changes in the margin will not change the error rates noticeably. However, the verify level control issue for M-bit/cell flash memories is more important and complex than that for SLC. This is because 2^{ M } states have to be crammed within the given constrained threshold voltage window W . More states will significantly reduce the margin between states and bit error rates (BER) will vary in response to small changes in verify levels. Furthermore, the number of verify levels which ISPP has to control increases from 1 (for SLC) to 2^{ M }−1 (for M-bit/cell MLC). In addition, as explained in the following, the multipage architecture of MLC flash memories makes verify level control more complex than SLC.
Most MLC flash memories adopt the multipage architecture. The important property of the multipage architecture is that different bits of a single cell are assigned into different pages[10–15]. Therefore, BERs of each page can be different. As a page is the unit of data that is programmed and read at one time, the error control coding (ECC) should be applied within the same page. It means that each page is composed of one or several codewords. Therefore, ECC has to be designed for the worst page BER and this leads to wasted redundancy for the other (i.e., better) pages. This uneven page BER problem is an important and practical issue and there have been several attempts to deal with it[11–15].
To deal with this different page BERs issue, we investigate two verify level control criteria for MLC flash memories. The first criterion is to minimize the overall BER. The second criterion is to make all page BERs equal[14]. These two criteria will be formulated as convex optimization problems. After solving these optimization problems, we will compare the numerical results from two criteria. In addition, the advantages and disadvantages of the two criteria will be discussed based on reliability, speed performance, and architecture of MLC flash memories. To the best of authors’ knowledge, the convex optimization approach for verify levels of ISPP has not been addressed in the open literature though experimental approaches could be investigated in industry.
An interesting way to combine the speed advantage of SLC and the cost advantage of MLC is to use a hybrid solid state drive (SSD) that judiciously uses both SLC and MLC flash memories. The basic idea of hybrid SSD is to complement the drawbacks of SLC and MLC with each other’s advantages[16–19]. Based on the architecture of the hybrid SSD and properties of the proposed verify level control criteria, we propose a strategy to apply the proper verify level control criterion for the hybrid SSD. This strategy is aimed at both reliability and speed performance.
The rest of this article is organized as follows: Section “Cell threshold voltage distribution” discusses the cell threshold voltage distribution under the assumption of a Gaussian mixture model (GMM). Based on this statistical model, the overall BER and the page BER are derived. Sections “Criteria for verify level control” and “ECC and flash memories of multipage architecture” address verify level control criteria and discuss their advantages and disadvantages for various MLCs (M = 2 ∼ 4) considering multipage architecture and ECC. Section “Hybrid SSD and strategy for verify level control” proposes a method to choose these criteria for the hybrid SSD based on reliability and speed performance. Finally, Section “Conclusion” concludes this article.
Cell threshold voltage distribution
where x refers to the threshold voltage and f_{ i }(x) is a Gaussian pdf with mean μ_{ i }and standard deviation σ_{ i }corresponding to the state S_{ i }. P(S_{ i }) is the probability of the state S_{ i }. If data size is sufficiently large and a scrambler is used, then we can assume that$P\left({S}_{0}\right)\approx \cdots \approx P\left({S}_{{2}^{M}-1}\right)\approx \frac{1}{{2}^{M}}$ with high probability.
where all Δ_{ k }s are positive since it is natural that μ_{i + 1}> μ_{ i }.
Most MLC flash memories adopt multipage architectures[10]. In this multipage architecture, ECC encoding and decoding are performed within each page. This means that pages with higher BERs will suffer from worse decoding failure rate. Therefore, the BER of each page could be more important than the overall BER in terms of ECC[11, 13–15].
Gray mapping for 2-bit/cell flash memories
State | S _{0} | S _{1} | S _{2} | S _{3} |
---|---|---|---|---|
page 1 | 1 | 1 | 0 | 0 |
page 2 | 1 | 0 | 0 | 1 |
Gray mapping for 3-bit/cell flash memories
State | S _{0} | S _{1} | S _{2} | S _{3} | S _{4} | S _{5} | S _{6} | S _{7} |
---|---|---|---|---|---|---|---|---|
page 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 |
page 2 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 |
page 3 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
Similarly, page BERs for 4-bit/cell or more could be derived from the mapping scheme provided.
where Δ_{ k }= Δ_{i,j}and ρ_{ k }= σ_{i,j} by k = 2i + j. Therefore,$\overrightarrow{\mathrm{\Delta}}$ and$\overrightarrow{\rho}$ will represent the all distances between states and the tightness of program states, respectively, and they will determine the overall BER and the page BERs. In the ISPP scheme,$\overrightarrow{\mathrm{\Delta}}$ can be controlled by verify levels and$\overrightarrow{\rho}$ by the incremental step size. In the following section, we will propose criteria for verify level control, which means how to determine$\overrightarrow{\mathrm{\Delta}}$ at the given$\overrightarrow{\rho}$.
Criteria for verify level control
We investigate two verify level control criteria. The first criterion is to minimize the overall BER, which is aimed at only reliability. The second criterion is to make page BERs equal considering both the reliability and the multipage architecture. These two criteria will be formulated as optimization problems. If the parameters of W(=μ_{2}^{ M }_{−1}−μ_{0}) and$\overrightarrow{\rho}$ are given,$\overrightarrow{\mathrm{\Delta}}=\left({\mathrm{\Delta}}_{1},\dots ,{\mathrm{\Delta}}_{2\left({2}^{M}-1\right)}\right)$ will be the variables of optimization problems.
We will show that the proposed criteria for verify level control are convex optimization problems. Therefore, the (globally) optimal solution can be efficiently found using numerical optimization techniques and the interior-point method was used to obtain the numerical results[25]. Also, mathematical conditions for the optimal solutions of these criteria are derived.
Criterion 1: minimize overall BER
where${g}_{1}\left(\overrightarrow{\mathrm{\Delta}}\right)=M{2}^{M}\xb7$ BER_{overall} by (5).
Since Δ_{ k } is the distance and ρ_{ k } is the standard deviation, all Δ_{ k }s and ρ_{ k }s are always positive. Therefore, (11) is a convex optimization problem and can be solved by several numerical methods[25].
Gray mapping for 4-bit/cell flash memories
State | S _{0} | S _{1} | S _{2} | S _{3} | S _{4} | S _{5} | S _{6} | S _{7} | S _{8} | S _{9} | S _{10} | S _{11} | S _{12} | S _{13} | S _{14} | S _{15} |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
page 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
page 2 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 |
page 3 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 |
page 4 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
BER _{ page 2 } /BER _{ page 1 } for 2-bit/cell flash memories ( W = 5)
σ | σ_{0}= σ | σ_{0}= 2σ | σ_{0}= 3σ | σ_{0}= 4σ |
---|---|---|---|---|
0.20 | 2.00 | 2.55 | 3.16 | 3.83 |
0.22 | 2.00 | 2.56 | 3.19 | 3.89 |
0.24 | 2.00 | 2.57 | 3.22 | 3.97 |
0.26 | 2.00 | 2.58 | 3.26 | 4.04 |
0.28 | 2.00 | 2.59 | 3.30 | 4.12 |
0.30 | 2.00 | 2.61 | 3.34 | 4.21 |
Criterion 2: make page BERs equal
In other words, even though the formulation in (18) does not explicitly set the page BERs to be identical, it implicitly minimizes the difference between all page BERs. Intuitively, if BER_{page m} is higher than other page BERs, the optimization in (18) will try to reduce BER_{page m} and make it as close to other page BERs as possible.
(18) is a convex optimization problem since ${h}_{m}\left(\overrightarrow{\mathrm{\Delta}}\right)$ is a nonnegative weighted sum of convex function Q(·). The convex property of Q(·) was shown in (12). Therefore, the optimal solution can be obtained by several numerical methods.
As discussed in criterion 1, all η_{ k }s will be zero due to complementary slackness of (21).
If one of λ s (for m = 0,…,M) is zero, then all λ_{ m }s should be zero since$\frac{\partial {G}_{2}}{\partial {\mathrm{\Delta}}_{k}}=0$ and$\frac{1}{\sqrt{2\Pi}{\rho}_{k}}exp\left(-\frac{{\mathrm{\Delta}}_{k}^{2}}{2{\rho}_{k}^{2}}\right)>0$ for all k. However, if all λ_{ m }s are zero, the condition of 1−λ_{1}−λ_{2} = 0 in (22) cannot hold. Therefore, we can see that λ_{ m }≠ 0, which results in h_{ m }−ε = 0 by KKT conditions of (21). It means that all page BERs will be equal for the optimal solution of (18)$\left(\because {h}_{m}\left(\overrightarrow{\mathrm{\Delta}}\right)={2}^{M}\xb7{\mathrm{BER}}_{\text{page}\phantom{\rule{1em}{0ex}}m}\right)$.
which are illustrated in Figure5.
Verify level control criteria and charge leakage
where μ_{pre} and$\left(\right)close="">{\sigma}_{\text{pre}}^{2}$ are the mean and the variance before charge leakage. μ_{post} and$\left(\right)close="">{\sigma}_{\text{post}}^{2}$ are the mean and the variance after charge leakage. μ_{shift} and$\left(\right)close="">{\sigma}_{\text{shift}}^{2}$ are the mean and the variance of threshold voltage shift by charge leakage. μ_{shift} and$\left(\right)close="">{\sigma}_{\text{shift}}^{2}$ depend on the program and erase (P/E) cycle count, retention time and temperature[6].
The proposed verify level control criteria should be applied based on μ_{post} and$\left(\right)close="">{\sigma}_{\text{post}}^{2}$ because μ_{post} and$\left(\right)close="">{\sigma}_{\text{post}}^{2}$ will determine the BER of flash memories. Therefore, we have to control μ_{pre} and$\left(\right)close="">{\sigma}_{\text{pre}}^{2}$ considering the amount of μ_{shift} and$\left(\right)close="">{\sigma}_{\text{shift}}^{2}$. Basically, μ_{pre} and$\left(\right)close="">{\sigma}_{\text{pre}}^{2}$ can be controlled by verify levels and the incremental step size ΔV_{ pp }of ISPP though physical mechanisms such as cell-to-cell interference, program disturbance, and background pattern dependency also affect μ_{pre} and$\left(\right)close="">{\sigma}_{\text{pre}}^{2}$[5, 7, 8].
Via chip testing, we can measure the amount of μ_{shift} and$\left(\right)close="">{\sigma}_{\text{shift}}^{2}$ as a function of P/E cycle count and retention time[6]. However, the allowable maximum values of μ_{shift} and$\left(\right)close="">{\sigma}_{\text{shift}}^{2}$ are generally used because ECC has to be designed to guarantee the reliability even in the worst case, which is also called end-of-life (EOL). EOL assumes the allowable maximum P/E cycle count and the allowable maximum retention time. Therefore, it is a practical method to apply the proposed verify level control criteria based on μ_{post} and$\left(\right)close="">{\sigma}_{\text{post}}^{2}$ of EOL. In this case, μ_{post} and$\left(\right)close="">{\sigma}_{\text{post}}^{2}$ should be used to formulate the convex optimization problems shown in (11) and (18). Other than this minor modification, no additional change is required for our proposed mathematical formulations.
Verify level control criteria and other statistical distributions
The distance between S_{ i }and S_{i + 1} will be defined as ν_{i + 1}−ν_{ i } instead of μ_{i + 1}−μ_{ i } and it is assumed that ν_{i + 1}> ν_{ i } for all i. In the case of Gaussian distributions, μ_{ i }and ν_{ i } are same.
where P(S_{ i }) is the probability of S_{ i }. In addition, Δ_{i,1} is the distance from ν_{ i }to D_{i,i + 1} and Δ_{i + 1,0} is the distance from ν_{i + 1} to D_{i,i + 1}. D_{i,i + 1} is the decision level between S_{ i }and S_{i + 1}.
where ϕ_{i,−}(t) = ϕ_{ i }(t + (ν_{ i }−ν_{0})) and ϕ_{i + 1, +}(t) = ϕ_{i + 1}(t−(ν_{2}^{ M }_{−1}−ν_{i + 1})). ν_{0} and ν_{2}^{ M }_{−1} are fixed value by (26).
The overall BER and the page BERs of M-bit/cell MLC flash memories are nonnegative weighted sums of E_{i,i + 1} for i = 0,…,2^{ M }−2. Therefore, if E_{i,i + 1} is a convex function of Δ_{i,1}and Δ_{i + 1,0}, the proposed verify level control criteria will be convex optimization problems.
The Hessian matrix of E_{i,i + 1}is given by
which mean that ϕ_{ i }(x) should be a unimodal distribution for convex optimization.
Since the measured threshold voltage distributions of recent flash memory products[2–4] are unimodal, the proposed verify level control criteria can be effectively applied to flash memories. In addition, the proposed verify level control criteria can be applied to other memories such as phase change memory (PCM) because the measured distributions of PCM in literature seem to be unimodal[26–28]. Especially,[26] claims that the distributions of PCM could be approximated by the log-normal distribution in spite of the anomalous tail. Therefore, our proposed verify level control criteria are expected to be useful in PCM.
ECC and flash memories of multipage architecture
where n is the codeword length and t is the error correcting capability. The bound becomes an equality when the decoder corrects all combinations of errors up to and including t errors, but no combinations of errors greater than t (i.e., bounded distance decoder)[29, 30]. In this article, the bounded distance decoder will be considered. Once ECC parameters such as n and t are selected, the WER is a function of only p.
Though errors in flash memories are generally not symmetric, the asymmetric component of errors could be minimized if the decision level are selected appropriately[22–24]. For example, for 2-bit/cell flash memories, the errors of page 1 will be symmetric if we select the decision level${\hat{D}}_{1,2}$ between S_{1} and S_{2} which makes$Q\left(\frac{{\mathrm{\Delta}}_{1,1}}{{\sigma}_{1,1}}\right)=Q\left(\frac{{\mathrm{\Delta}}_{2,0}}{{\sigma}_{2,0}}\right)$ in (6). Similarly, the errors of page 2 can be symmetric if we choose the decision levels${\hat{D}}_{0,1}$ and${\hat{D}}_{2,3}$ which make$Q\left(\frac{{\mathrm{\Delta}}_{0,1}}{{\sigma}_{0,1}}\right)=Q\left(\frac{{\mathrm{\Delta}}_{1,0}}{{\sigma}_{1,0}}\right)$ and$Q\left(\frac{{\mathrm{\Delta}}_{2,1}}{{\sigma}_{2,1}}\right)=Q\left(\frac{{\mathrm{\Delta}}_{3,0}}{{\sigma}_{3,0}}\right)$ in (6).
Although σ_{ i }≠ σ_{i + 1}, if σ_{ i } is not substantially different from σ_{i + 1}, the difference between D_{i,i + 1} and${\hat{D}}_{i,i+1}$ is almost negligible[22]. Therefore, the BER based on${\hat{D}}_{i,i+1}$ is similar to that based on D_{i,i + 1}. Considering these, we will use (31) to calculate the WER of flash memories[31].
where WER(BER_{page m}) is the WER of page m.
Theorem 1
If$0<=p<=\frac{t}{n-1}$, then WER(p) of (31) is a convex function of p.
Proof
□
Therefore,$\frac{{d}^{2}\mathrm{WER}(p)}{d{p}^{2}}>=0$ when$0<=p<=\frac{t}{n-1}$. □
(3) reveals that the overall WER would be improved by interleaving. If the interleaver is applied for the whole data from page 1 to page M, all page BERs will be averaged into the overall BER of (8) and the overall WER would be improved according to (34). In other words, minimizing the overall BER (i.e., criterion 1) is preferred over achieving identical page BERs (i.e., criterion 2), if interleaving is applied.
Actually, the application of interleaving and similar ideas have been proposed in order to resolve the uneven page BER problem and improve the reliability[11, 12]. However, the adoption of interleaving will slow down the program and read speed performance because the interleaver should wait to collect at least M pages data before program and read operation in the multipage architecture. Especially, random speed performance would be more degraded than sequential speed performance when employing an interleaver (see Section “Hybrid SSD and strategy for verify level control”).
Hybrid SSD and strategy for verify level control
In order to reduce the cost of SSD and maintain the speed performance and the durability, the hybrid SSD has been proposed[16, 17]. The basic idea is to use both SLC flash memories and MLC (usually 2-bit/cell) flash memories. The SLC flash memory has an edge over the MLC flash memory in terms of the speed performance and the durability. However, the MLC flash memory is cheaper than the SLC flash memory. Therefore, combining them can allow both types of flash memories to complement each other[16–19].
Recently, many flash translation layer (FTL) mapping schemes classify incoming data into hot and cold based on the access frequency and size. If a data is updated frequently, it is referred to as hot, and otherwise cold. Generally, small data are accessed more often, and they are classified as hot data. Meanwhile, cold data correspond to bulk writes at low frequencies[16, 18]. The speed performance of SSD is classified into random speed performance and sequential speed performance. The random speed performance is measured in input/output operations per second (IOPS) and the sequential speed performance is measured by transfer rate or throughput such as MB/sec[33]. Considering the characteristics of hot and cold data, we see that the random speed performance is a pivotal factor for hot data and the sequential speed performance is important for cold data.
Based on this architecture of the hybrid SSD, we propose that criterion 1 with interleaving is suitable for storing cold data in MLC because the interleaving would have only a small impact on the sequential speed performance for the cold data access and the garbage collection. Of course, we do not need to consider the verify level control criterion for SLC.
In addition, we can anticipate a lower cost and high density hybrid SSD which combines two types of MLC flash memories. For example, 2-bit/cell may replace SLC and 4-bit/cell may be used in place of 2-bit/cell. Unlike the conventional hybrid SSD which combines SLC and MLC of 2-bit/cell, we have to consider the verify level control criterion for both hot and cold data. We propose that criterion 2 will be appropriate for 2-bit/cell flash memories which mainly deal with hot data. For 4-bit/cell which usually stores cold data, criterion 1 with interleaving will be suitable considering the sequential speed performance and the reliability.
Conclusion
In this article, we investigated the verify level control criteria of ISPP for MLC flash memories. These criteria are formulated and solved by convex optimization. Criterion 1 can minimize the overall BER, however it requires interleaving in multipage architecture which reduces the speed performance. Criterion 2 is suitable for multipage architecture especially for 2-bit/cell flash memories. The problem of criterion 2 is that the error rate degradation will increase for more bits per cell.
Based on these advantages and disadvantages of verify level criteria, we investigated the application of verify level control criteria for the hybrid SSD. By selecting the proper criterion considering the architecture of the hybrid SSD, we can achieve both reliability and speed performance.
The verify level control criteria and the proposed formulation of optimization problems can be extended to other emerging memories such as PCM which are modeled by unimodal distributions.
Declarations
Authors’ Affiliations
References
- Prall K: Scaling non-volatile memory below 30nm,. IEEE 22nd Non-Volatile Semiconductor Memory Workshop pp. 5–10 (2007)Google Scholar
- Park K-T, Kwon O, Yoon S, Choi M-H, Kim I-M, Kim B-G, Kim M-S, Choi Y-H, Shin S-H, Song Y, Park J-Y, Lee J-E, Eun C-G, Lee H-C, Kim H-C, Lee J-H, Kim J-Y, Kweon T-M, Yoon H-J, Kim T, Shim D-K, Sel J, Shin J-Y, Kwak P, Han J-M, Kim K-S, Lee S, Lim Y-H, Jung T-S: A 7MB/s 64Gb 3-bit/cell DDR NAND flash memory in 20nm-node technology,. ISSCC Dig. Tech Papers pp. 212–213 (2011)Google Scholar
- T Kim S-D, Lee J, Park H, Cho B, You K, Baek J, Lee C, Yang M, Yun M, Kim J, Kim E, Jang H, Chung S, Lim B-S, Han Y-H, Koh A: 32Gb MLC NAND flash memory with Vth margin-expanding schemes in 26nm CMOS,. ISSCC Dig. Tech Papers pp. 202–204 (2011)Google Scholar
- Trinh C, Shibata N, Nakano T, Ogawa M, Sato J, Takeyama Y, Isobe K, Le B, Moogat F, Mokhlesi N, Kozakai K, Hong P, Kamei T, Iwasa K, Nakai J, Shimizu T, Honma M, Sakai S, Kawaai T, Hoshi S, Yuh J, Hsu C, Tseng T, Li J, Hu J, Liu M, Khalid S, Chen J, Watanabe M, Lin H, et al.: A 5.6MB/s 64Gb 4b/cell, NAND flash memory in 43nm CMOS,. ISSCC Dig. Tech. Papers pp. 245–246 (2009)Google Scholar
- Lee J-D, Hur S-H, Choi J-D: Effects of floating-gate interference on NAND flash memory cell operation. IEEE Electron. Device Lett 2002, 23(5):264-266.View ArticleGoogle Scholar
- Mielke N, Belgal H, Kalastirsky I, Kalavade P, Kurtz A, Meng Q, Righos N, Wu J: Flash EEPROM threshold instabilities due to charge trapping during program/erase cycling. IEEE Trans. Device Mater. Reliab 2004, 4(3):335-344. 10.1109/TDMR.2004.836721View ArticleGoogle Scholar
- Suh K-D, Suh B-H, Lim Y-H, Kim J-K, Choi Y-J, Koh Y-N, Lee S-S, Kwon S-C, Choi B-S, Yum J-S, Choi J-H, Kim J-R, Lim H-K: A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme. IEEE J. Solid-State Circ 1995, 30(11):1149-1156. 10.1109/4.475701View ArticleGoogle Scholar
- Jung T-S, Choi Y-J, Suh K-D, Suh B-H, Kim J-K, Lim Y-H, Koh Y-N, Park J-W, Lee K-J, Park J-H, Park K-T, Kim J-R, Lee J-H, Lim H-K: A 117-mm2 3.3-V only 128-Mb multilevel NAND flash memory for mass storage applications. IEEE J. Solid-State Circ 1996, 31(11):1575-1583. 10.1109/JSSC.1996.542301View ArticleGoogle Scholar
- Dong G, Xie N, Zhang T: On the use of soft-decision error-correction codes in NAND flash memory. IEEE Trans. Circ. Syst. I 2011, 58(2):429-439.MathSciNetView ArticleGoogle Scholar
- Takeuchi K, Tanaka T, Tanzawa T: A multipage cell architecture for high-speed programming multilevel NAND flash memories. IEEE J. Solid-State Circ 1998, 33: 1228-1238. 10.1109/4.705361View ArticleGoogle Scholar
- Murrin M: U.S. patent 7, 493, 457. 2009.Google Scholar
- Litsyn S, Alrod I, Sharon E, Murin M, Lasser M: U.S. patent 7, 681, 109. 2010.Google Scholar
- Lasser M: U.S. patent 8, 055, 972. 2011.Google Scholar
- Park SC, Eun H, Song S-H, Kong JJ, Chae DH: U.S. patent 7, 983, 082. 2011.Google Scholar
- Dong G, Xie N, Zhang T: Techniques for embracing intra-cell unbalanced bit error characteristics in MLC NAND flash memory,. IEEE Globecom Workshop on Application of Communication Theory to Emerging Memory Technologies pp. 1915–1920 (2010)Google Scholar
- Chang L-P: A hybrid approach to NAND-flash-based solid-state disks. IEEE Trans. Comput 2010, 59(10):1337-1349.MathSciNetView ArticleGoogle Scholar
- Chang L-P: Hybrid solid-state disks: Combining heterogeneous NAND flash in large SSDs,. Asia and South Pacific Design Automation Conference (ASPDAC) pp 428–433 (2008)Google Scholar
- Jung S, Kim J, Song Y: Hierarchical architecture of flash-based storage systems for high performance and durability,. 46th annual Design Automation Conference (DAC) pp. 907–910 (2009)Google Scholar
- Duann N: SLC and MLC hybrid. Flash Memory Summit (2008)Google Scholar
- Kencke DL, Richart R, Garg S, Banerjee SK: A multilevel approach toward quadrupling the density of flash memory. IEEE Electron. Device Lett 1998, 19: 86-88.View ArticleGoogle Scholar
- Wang J, Courtade T, Shankar H, Wesel RD: Soft information for LDPC decoding in flash: mutual-information optimized quantization,. IEEE Global Communications Conference pp. 5–9 (2011)Google Scholar
- Agrawal GP: Fiber-Optic Communication Systems,. 3rd edn. (Wiley, New York, 2002)View ArticleGoogle Scholar
- Kim YJ, Kim JH, Kong JJ, Son HR, Song SH: U.S. patent application, publication no 2010/0296350 (2010).Google Scholar
- Zhou H, Jiang A, Bruck J: Error-correcting schemes with dynamic thresholds in nonvolatile memories,. IEEE Int. Symposium on Information Theory (ISIT) 2109–2113 (2011)Google Scholar
- Boyd S, Vandenberghe L: Convex Optimization. (Cambridge University Press, Cambridge, 2004)View ArticleGoogle Scholar
- Mantegazza D, Ielmini D, Pirovano A, Gleixner B, Lacaita AL, Varesi E, Pellizzer F, Bez R: Electrical characterization of anomalous cells in phase change memory arrays,. IEEE International Electron Devices Meeting (IEDM) pp. 1–4 (2006)Google Scholar
- Bedeschi F, Fackenthal R, Resta C, Donze EM, Jagasivamani M, Buda EC, Pellizzer F, Chow DW, Cabrini A, Calvi GMA, Faravelli R, Fantini A, Torelli G, Mills D, Gastaldi R, Casagrande G: A bipolar-selected phase change memory featuring multi-level cell stroage. IEEE J. Solid-State Circ 2009, 44(1):217-227.View ArticleGoogle Scholar
- Servalli G: A 45nm generation phase change memory technology,. IEEE International Electron Devices Meeting (IEDM) pp. 1–4 (2009)Google Scholar
- Lin S, Costello Jr. DJ: Error Control Coding: Fundamentals and Applications,. 2nd edn. (Pearson Prentice-Hall, Upper Saddle River, 2004)Google Scholar
- Sklar B: Digital Communications Fundamentals and Applications,. 2nd edn. (Pearson Prentice-Hall, Upper Saddle River, 2001)Google Scholar
- Mielke N, Wu T, Kessenich J, Schares H, Trivedi E, Goodness F, Nevill E, Leland R: Bit error rate in NAND flash memories,. IEEE International Reliability Physics Symposium (IRPS) pp. 9–19 (2008)Google Scholar
- Press WH, Flannery BP, Teukolsky SA, Vetterling WT: Numerical Recipes,. 3rd edn. (Cambridge University Press, New York, 2007)Google Scholar
- Narayanan D, Thereska E, Donnelly A, Elnikety S, Rowstron A: Migrating enterprise storage to SSDs: analysis of tradeoffs,. 4th ACM European Conference on Computer Systems (EuroSys) 145–158 (2009)Google Scholar
Copyright
This article is published under license to BioMed Central Ltd. This is an Open Access article distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.