Open Access

A Partitioning Methodology That Optimises the Area on Reconfigurable Real-Time Embedded Systems

  • Camel Tanougast1Email author,
  • Yves Berviller1,
  • Serge Weber1 and
  • Philippe Brunet1
EURASIP Journal on Advances in Signal Processing20032003:743410

DOI: 10.1155/S1110865703212051

Received: 27 February 2002

Published: 20 May 2003

Abstract

We provide a methodology used for the temporal partitioning of the data-path part of an algorithm for a reconfigurable embedded system. Temporal partitioning of applications for reconfigurable computing systems is a very active research field and some methods and tools have already been proposed. But all these methodologies target the domain of existing reconfigurable accelerators or reconfigurable processors. In this case, the number of cells in the reconfigurable array is an implementation constraint and the goal of an optimised partitioning is to minimise the processing time and/or the memory bandwidth requirement. Here, we present a strategy for partitioning and optimising designs. The originality of our method is that we use the dynamic reconfiguration in order to minimise the number of cells needed to implement the data path of an application under a time constraint. This approach can be useful for the design of an embedded system. Our approach is illustrated by a reconfigurable implementation of a real-time image processing data path.

Keywords

partitioning FPGA implementation reconfigurable systems on chip

Authors’ Affiliations

(1)
Laboratoire d'Instrumentation Electronique de Nancy, Université de Nancy I

Copyright

© Copyright © 2003 Hindawi Publishing Corporation 2003