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Floating-to-Fixed-Point Conversion for Digital Signal Processors

Abstract

Digital signal processing applications are specified with floating-point data types but they are usually implemented in embedded systems with fixed-point arithmetic to minimise cost and power consumption. Thus, methodologies which establish automatically the fixed-point specification are required to reduce the application time-to-market. In this paper, a new methodology for the floating-to-fixed point conversion is proposed for software implementations. The aim of our approach is to determine the fixed-point specification which minimises the code execution time for a given accuracy constraint. Compared to previous methodologies, our approach takes into account the DSP architecture to optimise the fixed-point formats and the floating-to-fixed-point conversion process is coupled with the code generation process. The fixed-point data types and the position of the scaling operations are optimised to reduce the code execution time. To evaluate the fixed-point computation accuracy, an analytical approach is used to reduce the optimisation time compared to the existing methods based on simulation. The methodology stages are described and several experiment results are presented to underline the efficiency of this approach.

References

  1. Grötker T, Multhaup E, Mauss O: Evaluation of HW/SW tradeoffs using behavioral synthesis. Proceeding of 7th International Conference on Signal Processing Applications and Technology (ICSPAT '96), October 1996, Boston, Mass, USA 781–785.

    Google Scholar 

  2. Kum K-I, Kang J, Sung W: AUTOSCALER for C: an optimizing floating-point to integer C program converter for fixed-point digital signal processors. IEEE Transactions on Circuits and SystPart II 2000, 47(9):840–848. 10.1109/82.868453

    Article  Google Scholar 

  3. Willems M, Bursgens V, Meyr H: FRIDGE: floating-point programming of fixed-point digital signal processors. Proceeding of 8th International Conference on Signal Processing Applications and Technology (ICSPAT '97), September 1997, San Diego, Calif, USA

    Google Scholar 

  4. Menard D, Quemerais P, Sentieys O: Influence of fixed-point DSP architecture on computation accuracy. Proceeding of 11th European Signal Processing Conference (EUSIPCO '02), September 2002, Toulouse, France 1: 587–590.

    Google Scholar 

  5. Kim S, Sung W: A floating-point to fixed-point assembly program translator for the TMS 320C25. IEEE Transactions on Circuits and SystemsPart II 1994, 41(11):730–739. 10.1109/82.331543

    Google Scholar 

  6. Keding H, Willems M, Coors M, Meyr H: FRIDGE: a fixed-point design and simulation environment. Proceeding of IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE '98), February 1998, Paris, France 429–435.

    Google Scholar 

  7. Willems M, Bursgens V, Keding H, Grötker T, Meyr H: System level fixed-point design based on an interpolative approach. Proceeding of 34th ACM/IEEE Design Automation Conference (DAC '97), June 1997, Anaheim, Calif, USA 293–298.

    Chapter  Google Scholar 

  8. Kum K-I, Kang J, Sung W: A floating-point to integer C converter with shift reduction for fixed-point digital signal processors. Proceeding of IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '99), March 1999, Phoenix, Ariz, USA 4: 2163–2166.

    Google Scholar 

  9. Kim S, Sung W:Fixed-point error analysis and word length optimization of IDCT architectures. IEEE Transactions on Circuits and Systems for Video Technology 1998, 8(8):935–940. 10.1109/76.736720

    Article  Google Scholar 

  10. Kim S, Kum K-I, Sung W: Fixed-point optimization utility for C and C++ based digital signal processing programs. IEEE Transactions on Circuits and SystemsPart II 1998, 45(11):1455–1464. 10.1109/82.735357

    Article  Google Scholar 

  11. De Coster L, Ade M, Lauwereins R, Peperstraete J: Code generation for compiled bit-true simulation of DSP applications. Proceeding of 11th IEEE International Symposium on System Synthesis (ISSS '98), December 1998, Hsinchu, Taiwan 9–14.

    Google Scholar 

  12. Keding H, Coors M, Lüthje O, Meyr H: Fast bit-true simulation. Proceeding of 38th ACM/IEEE Design Automation Conference (DAC '01), June 2001, Las Vegas, Nev, USA 708–713.

    Google Scholar 

  13. Keding H, Hurtgen F, Willems M, Coors M: Transformation of floating-point into fixed-point algorithms by interpolation applying a statistical approach. Proceeding of 9th International Conference on Signal Processing Applications and Technology (ICSPAT '98), September 1998, Toronto, Ontario, Canada

    Google Scholar 

  14. Menard D, Sentieys O: Automatic evaluation of the accuracy of fixed-point algorithms. Proceeding of IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE '02), March 2002, Paris, France 529–535.

    Google Scholar 

  15. Wilson R: SUIF: an infrastructure for research on parallelizing and optimizing compilers. In Tech. Rep. CA 94305-4055. Computer Systems Laboratory, Stanford University, Stanford, Calif, USA; May 1994.

    Google Scholar 

  16. Charot F, Djieya F, Wagner C: Retargetable compilation in the service of interactive ASIP design. In Tech. Rep. 1173. Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Rennes, France; November 2000.

    Google Scholar 

  17. Charot F, Messe V: A flexible code generation framework for the design of application specific programmable processors. Proceeding of 7th IEEE International Workshop on Hardware/Software Codesign (CODES '99), May 1999, Rome, Italy 27–31.

    Chapter  Google Scholar 

  18. Madisetti V: VLSI Digital Signal Processors: An Introduction to Rapid Prototyping and Design Synthesis . IEEE Press/Butterworth-Heinemann, Boston, Mass, USA; 1995.

    MATH  Google Scholar 

  19. Menard D, Rocher R, Scalart P, Sentieys O: SQNR determination in non-linear and non-recursive fixed-point systems. Proceeding of 12th European Signal Processing Conference (EUSIPCO '04), September 2004, Vienna, Austria 1349–1352.

    Google Scholar 

  20. Constantinides GA, Cheung PYK, Luk W: Truncation noise in fixed-point SFGs. IEE Electronics Letters 1999, 35(23):2012–2014. 10.1049/el:19991375

    Article  Google Scholar 

  21. Kearfott R: Interval computations: introduction, uses, and resources. Euromath Bulletin 1996, 2(1):95–112.

    MathSciNet  Google Scholar 

  22. Parks TW, Burrus CS: Digital Filter Design. John Wiley & Sons, New York, NY, USA; 1987.

    MATH  Google Scholar 

  23. Texas Instruments Incorporated : TMS320C54x DSP Reference Set, Volume 1: CPU And Peripherals. Texas Instruments, Dallas, Tex, USA, January 1999

    Google Scholar 

  24. Lucent Technologies : DSP16xx. Lucent Technologies, Murray Hill, NJ, USA

  25. Lapsley P, Bier J, Shoham A, Lee EA: DSP Processor Fundamentals: Architectures and Features. Berkeley Design Technology, Fremont, Calif, USA; 1996.

    MATH  Google Scholar 

  26. Ovadia B, Wertheizer G: PalmDSPCore—Dual MAC and parallel modular architecture. In Proceeding of 10th International Conference on Signal Processing Applications and Technology (ICSPAT '99), November 1999, Orlando, Fla, USA. Miller Freeman;

    Google Scholar 

  27. Efstathiou D, Fridman L, Zvonar Z: Recent developments in enabling technologies for software defined radio. IEEE Communications Magazine 1999, 37(8):112–117. 10.1109/35.783134

    Article  Google Scholar 

  28. Analog Device Incorporation : TigerSHARC Hardware Specification. Analog Device, December 1999

    Google Scholar 

  29. Texas Instruments Incorporated : TMS320C64x Technical Overview. Texas Instruments, Dallas, Tex, USA, February 2000

    Google Scholar 

  30. 3DSP : SP-5 Fixed-point Signal Processor Core. 3DSP Corporation, Irvine, Calif, USA, July 1999

    Google Scholar 

  31. CEVA Incorporation : CEVA-X1620 Datasheet. CEVA, San Jose, Calif, USA, 2004

    Google Scholar 

  32. Wichman S, Goel N: The Second Generation ZSP DSP. LSI Logic Corporation, Milpitas, Calif, USA, 2002

    Google Scholar 

  33. Ghazal N, Newton R, Rabaey J: Predicting performance potential of modern DSPs. Proceeding of 37th ACM/IEEE Design Automation Conference (DAC '00), June 2000, Los Angeles, Calif, USA 332–335.

    Chapter  Google Scholar 

  34. Pegatoquet A, Gresset E, Auguin M, Bianco L: Rapid development of optimized DSP code from a high level description through software estimations. Proceeding of 36th ACM/IEEE Design Automation Conference (DAC '99), June 1999, New Orleans, La, USA 823–826.

    Chapter  Google Scholar 

  35. Fletcher R: Practical Methods of Optimization. 2nd edition. John Wiley & Sons, New York, NY, USA; 1987.

    MATH  Google Scholar 

  36. Texas Instruments Incorporated : TMS320C5x User's Guide. Texas Instruments, Dallas, Tex, USA, June 1998

    Google Scholar 

  37. Zivojnovic V, Velarde JM, Schläger C, Meyr H: DSPStone: A DSP-oriented benchmarking methodology. In Proceeding of 5th International Conference on Signal Processing Applications and Technology (ICSPAT '94), October 1994, Dallas, Tex, USA. Miller Freeman; 715–720.

    Google Scholar 

  38. VLSI Technology : VVF 3500 DSP Core Rev. 1.2. VLSI Technology, June 1998

    Google Scholar 

  39. Li Y-TS, Malik S: Performance analysis of embedded software using implicit path enumeration. Proceeding of 32nd ACM/IEEE Design Automation Conference (DAC '95), June 1995, San Francisco, Calif, USA 456–461.

    Chapter  Google Scholar 

  40. Ojanperä T, Prasad R (Eds): WCDMA: Towards IP Mobility and Mobile Internet, Universal Personal Communications Series. Artech House, Norwood, Mass, USA; 2002.

    Google Scholar 

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Correspondence to Daniel Menard.

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Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License ( https://creativecommons.org/licenses/by/2.0 ), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Menard, D., Chillet, D. & Sentieys, O. Floating-to-Fixed-Point Conversion for Digital Signal Processors. EURASIP J. Adv. Signal Process. 2006, 096421 (2006). https://doi.org/10.1155/ASP/2006/96421

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