Skip to main content
EURASIP Journal on Advances in Signal Processing
Download PDF
  • Research Article
  • Open access
  • Published:

3D-SoftChip: A Novel Architecture for Next-Generation Adaptive Computing Systems

EURASIP Journal on Advances in Signal Processing volume 2006, Article number: 075032 (2006) Cite this article

Abstract

This paper introduces a novel architecture for next-generation adaptive computing systems, which we term 3D-SoftChip. The 3D-SoftChip is a 3-dimensional (3D) vertically integrated adaptive computing system combining state-of-the-art processing and 3D interconnection technology. It comprises the vertical integration of two chips (a configurable array processor and an intelligent configurable switch) through an indium bump interconnection array (IBIA). The configurable array processor (CAP) is an array of heterogeneous processing elements (PEs), while the intelligent configurable switch (ICS) comprises a switch block, 32-bit dedicated RISC processor for control, on-chip program/data memory, data frame buffer, along with a direct memory access (DMA) controller. This paper introduces the novel 3D-SoftChip architecture for real-time communication and multimedia signal processing as a next-generation computing system. The paper further describes the advanced HW/SW codesign and verification methodology, including high-level system modeling of the 3D-SoftChip using SystemC, being used to determine the optimum hardware specification in the early design stage.

References

  1. Goldstein SC, Schmit H, Budiu M, Cadambi S, Moe M, Taylor RR: PipeRench: a reconfigurable architecture and compiler. IEEE Computer 2000, 33(4):70–77. 10.1109/2.839324

    Article  Google Scholar 

  2. Singh H, Lee M-H, Lu G, Kurdahi FJ, Bagherzadeh N, Chaves Filho EM: MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications. IEEE Transactions on Computers 2000, 49(5):465–481. 10.1109/12.859540

    Article  Google Scholar 

  3. Miyamori T, Olukotun K: REMARC: reconfigurable multimedia array coprocessor. Proceedings of ACM/SIGDA 6th International Symposium on Field Programmable Gate Arrays (FPGA '98), February 1998, Monterey, Calif, USA 261–261.

    Google Scholar 

  4. Elixent Limited : The Reconfigurable Algorithm Processor. https://doi.org/www.elixent.com/products/white_papers.htm

  5. Tredennick N, Shimamoto B: Special Report: do-it-all devices. IEEE Spectrum December 2003, 37–40.

    Google Scholar 

  6. Joyner JW, Zarkesh-Ha P, Meindl JD: Global interconnect design in a three-dimensional system-on-a-chip. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2004, 12(4):367–372.

    Article  Google Scholar 

  7. Eshraghian S, Lachowicz S, Eshraghian K: 3-D vertically integrated configurable soft-chip with terabit computational bandwidth for image and data processing. Proceedings of 10th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES '03), June 2003, Lodz, Poland 143–148.

    Google Scholar 

  8. Rassau A, Alagoda G, Ehrhardt A, Lachowicz S, Eshraghian K: Design methodology for a 3D softchip video processing architecture. Proceedings of 6th World Multiconference on Systemics, Cybernetics and Informatics (SCI '02), July 2002, Orlando, Fla, USA 324–329.

    Google Scholar 

  9. IZM : 3D System Integration. https://doi.org/www.pb.izm.fhg.de/izm/015_Programms/010_R/

  10. Joyner JW, Venkatesan R, Zarkesh-Ha P, Davis JA, Meindl JD: Impact of three-dimensional architectures on interconnects in gigascale integration. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2001, 9(6):922–928.

    Article  Google Scholar 

  11. Chen D, Rabaey J: PADDI: programmable arithmetic devices for digital signal processing. In Proceedings of IEEE Workshop on VLSI Signal Processing, November 1990, San Diego, Calif, USA. IEEE Press; 240–249.

    Google Scholar 

  12. Mirsky E, DeHon A: MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources. Proceedings of IEEE Symposium on FPGAs for Custom Computing Machines, April 1996, Napa Valley, Calif, USA 157–166.

    Chapter  Google Scholar 

  13. Cronquist DC, Fisher C, Figueroa M, Franklin P, Ebeling C: Architecture design of reconfigurable pipelined datapaths. Proceedings of 20th Anniversary Conference on Advanced Research in VLSI (ARVLSI '99), March 1999, Atlanta, Ga, USA 23–40.

    Chapter  Google Scholar 

  14. Waingold E, Taylor M, Srikrishna D, et al.: Baring it all to software: raw machines. IEEE Computer 1997, 30(9):86–93. 10.1109/2.612254

    Article  Google Scholar 

  15. Triscend Corporation : Triscend A7S Configurable System-on-Chip Platforms. https://doi.org/www.triscend.com

  16. Motorola Incorporation : MRC6100: Reconfigurable Compute Fabric (RCF) device. https://doi.org/www.motorola.com/semiconductors/

  17. QuickSilver Technology Incorporation : Adapt2400 ACM Architecture Overview.

  18. picoChip Designs Limited : PC102 Product Brief. https://doi.org/www.picochip.com

  19. Guangming L: Modeling, implementation and scalability of the morphoSys dynamically reconfigurable computing architecture, M.S. thesis. Electrical and Computer Engineering Department, University of California, Irvine, Calif, USA; 2000.

    Google Scholar 

  20. Eshraghian S: Implementation of arithmetic primitives using truly deep submicron technology (TDST), Ms thesis. Edith Cowan University, Perth, Australia; 2004.

    Google Scholar 

  21. Open SystemC Initiative : The Functional Specification for SystemC 2.0. https://doi.org/www.systemc.org/

  22. Open SystemC Initiative : SystemC 2.0.1 Language Reference Manual Rev 1.0. https://doi.org/www.systemc.org/

Download references

Author information

Authors and Affiliations

  1. Centre for Very High Speed Microelectronic Systems, Edith Cowan University, Joondalup, WA, 6027, Australia

    Chul Kim, Alex Rassau & Stefan Lachowicz

  2. School of Information and Communication Engineering, Dongshin University, Naju, Chonnam, 520714, Korea

    Mike Myung-Ok Lee

  3. Eshraghian Laboratories Pty Ltd, Technology Park, Bentley, WA, 6102, Australia

    Kamran Eshraghian

Authors
  1. Chul Kim
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Alex Rassau
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Stefan Lachowicz
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Mike Myung-Ok Lee
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Kamran Eshraghian
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License ( https://creativecommons.org/licenses/by/2.0 ), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Reprints and permissions

About this article

Cite this article

Kim, C., Rassau, A., Lachowicz, S. et al. 3D-SoftChip: A Novel Architecture for Next-Generation Adaptive Computing Systems. EURASIP J. Adv. Signal Process. 2006, 075032 (2006). https://doi.org/10.1155/ASP/2006/75032

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • DOI: https://doi.org/10.1155/ASP/2006/75032

Keywords