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Multiple-Clock-Cycle Architecture for the VLSI Design of a System for Time-Frequency Analysis

EURASIP Journal on Advances in Signal Processing volume 2006, Article number: 060613 (2006) Cite this article

Abstract

Multiple-clock-cycle implementation (MCI) of a flexible system for time-frequency (TF) signal analysis is presented. Some very important and frequently used time-frequency distributions (TFDs) can be realized by using the proposed architecture: (i) the spectrogram (SPEC) and the pseudo-Wigner distribution (WD), as the oldest and the most important tools used in TF signal analysis; (ii) the S-method (SM) with various convolution window widths, as intensively used reduced interference TFD. This architecture is based on the short-time Fourier transformation (STFT) realization in the first clock cycle. It allows the mentioned TFDs to take different numbers of clock cycles and to share functional units within their execution. These abilities represent the major advantages of multicycle design and they help reduce both hardware complexity and cost. The designed hardware is suitable for a wide range of applications, because it allows sharing in simultaneous realizations of the higher-order TFDs. Also, it can be accommodated for the implementation of the SM with signal-dependent convolution window width. In order to verify the results on real devices, proposed architecture has been implemented with a field programmable gate array (FPGA) chips. Also, at the implementation (silicon) level, it has been compared with the single-cycle implementation (SCI) architecture.

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Authors and Affiliations

  1. Department of Electrical Engineering, University of Montenegro, Podgorica, Montenegro, 81000, Serbia and Montenegro

    Veselin N. Ivanović, Radovan Stojanović & L Jubivša Stanković

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  1. Veselin N. Ivanović
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  2. Radovan Stojanović
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  3. L Jubivša Stanković
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Correspondence to Veselin N. Ivanović.

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Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License ( https://creativecommons.org/licenses/by/2.0 ), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Ivanović, V.N., Stojanović, R. & Stanković, L.J. Multiple-Clock-Cycle Architecture for the VLSI Design of a System for Time-Frequency Analysis. EURASIP J. Adv. Signal Process. 2006, 060613 (2006). https://doi.org/10.1155/ASP/2006/60613

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  • DOI: https://doi.org/10.1155/ASP/2006/60613

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