Skip to main content
EURASIP Journal on Advances in Signal Processing
Download PDF
  • Research Article
  • Open access
  • Published:

Self-Timed Scheduling Analysis for Real-Time Applications

EURASIP Journal on Advances in Signal Processing volume 2007, Article number: 083710 (2007) Cite this article

Abstract

This paper deals with the scheduling analysis of hard real-time streaming applications. These applications are mapped onto a heterogeneous multiprocessor system-on-chip (MPSoC), where we must jointly meet the timing requirements of several jobs. Each job is independently activated and processes streams at its own rate. The dynamic starting and stopping of jobs necessitates the usage of self-timed schedules (STSs). By modeling job implementations using multirate data flow (MRDF) graph semantics, real-time analysis can be performed. Traditionally, temporal analysis of STSs for MRDF graphs only aims at evaluating the average throughput. It does not cope well with latency, and it does not take into account the temporal behavior during the initial transient phase. In this paper, we establish an important property of STSs: the initiation times of actors in an STS are bounded by the initiation times of the same actors in any static periodic schedule of the same job; based on this property, we show how to guarantee strictly periodic behavior of a task within a self-timed implementation; then, we provide useful bounds on maximum latency for jobs with periodic, sporadic, and bursty sources, as well as a technique to check latency requirements. We present two case studies that exemplify the application of these techniques: a simplified channel equalizer and a wireless LAN receiver.

References

  1. Buttazzo GC: Hard Real-Time Computing Systems. Kluwer Academic Publishers, Boston, Mass, USA; 1997.

    MATH  Google Scholar 

  2. Moonen AJM, van den Berg R, Bekooij MJG, Bhullar H, van Meerbergen J: A multi-core architecture for in-car digital entertainment. Proceedings of Global Signal Processing Conference & Expos for the Industry, October 2005, Santa Clara, Calif, USA

    Google Scholar 

  3. Goossens K, Dielissen J, Rǎdulescu A: Æthereal network on chip: concepts, architectures, and implementations. IEEE Design and Test of Computers 2005,22(5):414-421. 10.1109/MDT.2005.99

    Article  Google Scholar 

  4. Hansson A, Goossens K, Rǎdulescu A: A unified approach to constrained mapping and routing on network-on-chip architectures. Proceedings of International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '05), September 2005, Jersey City, NJ, USA 75–80.

    Google Scholar 

  5. Moreira OM, Mol JD, Bekooij MJG, van Meerbergen J: Multiprocessor resource allocation for hard-real-time streaming with a dynamic job-mix. Proceedings of IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS '05), March 2005, Francisco, Calif, USA 332–341.

    Google Scholar 

  6. Moreira OM, Bekooij MJG, Mol JD: Online resource mangement in a multiprocessor with a network-on-chip. Proceedings of the 22nd Annual ACM Symposium on Applied Computing (SAC '07), March 2007, Seoul, Korea

    Google Scholar 

  7. Lee EA, Messerschmitt DG: Synchronous data flow. Proceedings of the IEEE 1987,75(9):1235-1245.

    Article  Google Scholar 

  8. Sriram S, Bhattacharyya SS: Embedded Multiprocessors: Scheduling and Synchronization. Marcel Dekker, New York, NY, USA; 2000.

    Google Scholar 

  9. Bambha N, Kianzad V, Khandelia M, Bhattacharyya SS: Intermediate representations for design automation of multiprocessor DSP systems. Design Automation for Embedded Systems 2002,7(4):307-323. 10.1023/A:1020307222052

    Article  Google Scholar 

  10. Goddard S, Jeffay K: Managing latency and buffer requirements in processing graph chains. The Computer Journal 2001,44(6):486-503. 10.1093/comjnl/44.6.486

    Article  Google Scholar 

  11. Jersak M, Richter K, Ernst R: Performance analysis of complex embedded systems. International Journal of Embedded Systems 2005,1(1-2):33-49.

    Article  Google Scholar 

  12. Reiter R: Scheduling parallel computations. Journal of the ACM 1968,15(4):590-599. 10.1145/321479.321485

    Article  Google Scholar 

  13. Lee EA, Messerschmitt DG: Static scheduling of synchronous data flow programs for digital signal processing. IEEE Transactions on Computers 1987,36(1):24-35.

    Article  Google Scholar 

  14. Dasdan A: Experimental analysis of the fastest optimum cycle ratio and mean algorithms. ACM Transactions on Design Automation of Electronic Systems 2004,9(4):385-418. 10.1145/1027084.1027085

    Article  Google Scholar 

  15. Poplavko P, Basten T, Bekooij MJG, van Meerbergen J, Mesman B: Task-level timing models for guaranteed performance in multiprocessor networks-on-chip. Proceedings of International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES '03), October-November 2003, San Jose, Calif, USA 63–72.

    Chapter  Google Scholar 

  16. Baccelli F, Cohen G, Olsder G, Quadrat J-P: Synchronization and Linearity. John Wiley & Sons, New York, NY, USA; 1992.

    MATH  Google Scholar 

  17. Govindarajan R, Gao GR: A novel framework for multi-rate scheduling in DSP applications. Proceedings of International Conference on Application-Specific Array Processors, October 1993, Venice, Italy 77–88.

    Chapter  Google Scholar 

  18. Ghamarian AH, Geilen MCW, Stuijk S, et al.: Throughput analysis of synchronous data flow graphs. Proceedings of the 6th International Conference on Application of Concurrency to System Design (ACSD '06), June 2006, Turku, Finland 25–36.

    Chapter  Google Scholar 

  19. Corman TH, Leiserson CE, Rivest RL, Stein C: Introduction to Algorithms. McGraw-Hill, New York, NY, USA; 2001.

    Google Scholar 

  20. Moonen AJM, Bekooij MJG, van Meerbergen J: Timing analysis model for network based multiprocessor systems. Proceedings of the 15th Annual Workshop of Circuits, System and Signal Processing (ProRISC '04), November 2004, Veldhoven, The Netherlands 91–99.

    Google Scholar 

  21. Bekooij MJG, Hoes R, Moreira OM, et al.: Dataflow analysis for real-time embedded multiprocessor system design. In Dynamic and Robust Streaming in and between Connected Consumer Electronic Devices. Volume 3. Springer, New York, NY, USA; 2005:81-108. 10.1007/1-4020-3454-7_4

    Chapter  Google Scholar 

  22. Govindarajan R, Gao GR, Desai P: Minimizing memory requirements in rate-optimal schedules. Proceedings of International Conference on Application Specific Array Processors, August 1994, San Francisco, Calif, USA 75–86.

    Chapter  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. NXP Semiconductors Research, Eindhoven, 5656, AE, The Netherlands

    Orlando M. Moreira & Marco J. G. Bekooij

Authors
  1. Orlando M. Moreira
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Marco J. G. Bekooij
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Orlando M. Moreira.

Rights and permissions

Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License (https://doi.org/creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Reprints and permissions

About this article

Cite this article

Moreira, O.M., Bekooij, M.J.G. Self-Timed Scheduling Analysis for Real-Time Applications. EURASIP J. Adv. Signal Process. 2007, 083710 (2007). https://doi.org/10.1155/2007/83710

Download citation

  • Received:

  • Accepted:

  • Published:

  • DOI: https://doi.org/10.1155/2007/83710

Keywords